On the Extension of Single-core Thermal Models to Multi-core Platforms in Critical Real-Time Domains
Ref: CISTER-TR-190610 Publication Date: 2019
On the Extension of Single-core Thermal Models to Multi-core Platforms in Critical Real-Time DomainsRef: CISTER-TR-190610 Publication Date: 2019
The advent of multi-core platforms in critical real-time domains such as the avionics, automotive and railways to achieve higher and higher computing performance has turned the view on thermal concerns of the underlying chip die while it is still mandatory to meet all the temporal constraints. As a matter of fact, high chip temperature may not only degrade system performance and reliability, but it may also damage the chip permanently. In this paper, we propose a methodology to address this problem, based on fixed task-to-core mapping and per-core analysis to derive a sound system model without feedback loop. To this end, it is important to have a better and deeper understanding of the existing thermal models in the literature. This is the main contribution of this research.