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Publications

Publications

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Books & Book Chapters
Robot Path Planning and Cooperation - Foundations, Algorithms and Experimentations CISTER-TR-180202 
Anis Koubâa, Hachemi Bennaceur, Imen Chaari, Sahar Trigui, Adel Ammar, Mohamed-Foued Sriti, Maram Alajlan, Omar Cheikhrouhou, Yasir JavedTo be published. 2018, 400 pages.
Journal Papers
Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements CISTER-TR-170702 
Anna Minaeva, Benny Åkesson, Zdeněk Hanzálek, Dakshina Dasari
ABSTRACT Additional Files: PDFOpen Access Version
IEEE Transactions on Computers, IEEE. 1, Jan, 2018, Volume 67, Issue 1, pp 115-129.
Joint Beamforming, Terminal Scheduling, and Adaptive Modulation with Imperfect CSIT in Rice Fading Correlated Channels with non-persistent Co-channel Interference CISTER-TR-171103 
Ramiro RoblesTo be published in International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems (IJATES2), IARIA. 2018.
IEEE 802.15.4e in a Nutshell: Survey and Performance Evaluation CISTER-TR-180203 
Harrison Kurunathan, Ricardo Severino, Anis Koubâa, Eduardo TovarTo be published in IEEE Communications Surveys & Tutorials (COMST. 2018), IEEE. 2018.
Conference or Workshop Papers
LCD: Low Latency Command Dissemination for A Platoon of Vehicles CISTER-TR-180109 
Kai Li, Eduardo Tovar, Mohsen GuizaniAccepted in IEEE International Conference on Communications (ICC 2018). 20 to 24, May, 2018, AD HOC AND SENSOR NETWORKING SYMPOSIUM. Kansas, U.S.A..
Maintenance 4.0 World of Integrated Information CISTER-TR-180108 
Erkki Jantunen, Giovanni di Orio, Csaba Hegedus, Pal Varga, Istvan Moldovan, Felix Larrinaga, Matthias Becker, Michele Albano, Pedro MalóAccepted in Interoperability for Enterprise Systems and Applications (I-ESA 2018). 22 to 23, Mar, 2018. Berlin, Germany.
Converging Safety and High-performance Domains: Integrating OpenMP into Ada CISTER-TR-180201 
Sara Royuela, Luis Miguel Pinho, Eduardo QuiñonesAccepted in Design, Automation, and Test in Europe conference (DATE 2018). 19 to 21, Mar, 2018. Dresden, Germany.
Mixed-criticality Scheduling with Memory Bandwidth Regulation CISTER-TR-171201 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarAccepted in Design, Automation and Test in Europe 2018 (DATE 2018). 19 to 23, Mar, 2018. Dresden, Germany.
Performance analysis of superimposed training-based cooperative spectrum sensing CISTER-TR-171203 
Lizeth Lopez-Lopez, Marco Cardenas-Juarez, Enrique Stevens-Navarro, Abel Garcia, Rafael Aguilar-Gonzalez, Ramiro RoblesAccepted in 28th International Conference on Electronics, Communications and Computers (CONIELECOMP 2018). 21 to 23, Feb, 2018. Puebla, Mexico.
Conference or Workshop Posters/Demos
Multicore emulation-in-the-loop in the Khronosim project CISTER-TR-180112 
Luis Miguel PinhoDemo in 6th International workshop on the “Integration of mixed-criticality subsystems on multi-core and manycore processors” (MCS 2018). 23, Jan, 2018, Embedded parallel architectures for mixed-criticality. Manchester.MCS 2018 was held as part of the High Performance and Embedded Architecture and Compilation Conference (HiPEAC 2018), January 22-24, 2018.
Technical Reports
RPL over DSME: A Technical Report CISTER-TR-180110 
Harrison Kurunathan, Ricardo Severino, Anis Koubâa, Eduardo TovarAccepted in 2018.


Short link for this page: www.cister.isep.ipp.pt/docs/Y2018/