Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs
Ref: CISTER-TR-180408 Publication Date: 19 to 23, Mar, 2018
Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCsRef: CISTER-TR-180408 Publication Date: 19 to 23, Mar, 2018
This paper aims to reduce the pessimism of the analysis of the multi-point progressive blocking (MPB) problem in real-time priority-preemptive wormhole networks-on-chip. It shows that the amount of buffering on each network node can influence the worst-case interference that packets can suffer along their routes, and it proposes a novel analytical model that can quantify such interference as a function of the buffer size. It shows that, perhaps counter-intuitively, smaller buffers can result in lower upper-bounds on interference and thus improved schedulability. Didactic examples and large-scale experiments provide evidence of the strength of the proposed approach.
Design, Automation and Test in Europe Conference and Exhibition (DATE 2018), Track E: Embedded and Cyber-Physical Systems, pp 219-224.
Notes: Best Paper Award 2018