Response Time Analysis of COTS-Based Multicores Considering The Contention On The Shared Memory Bus
Ref: HURRAY-TR-110705 Publication Date: 16 to 18, Nov, 2011
Response Time Analysis of COTS-Based Multicores Considering The Contention On The Shared Memory BusRef: HURRAY-TR-110705 Publication Date: 16 to 18, Nov, 2011
Abstract—The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing realtime embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks is not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper proposes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst-case response time for a set of tasks. Finally, this paper describes a method to experimentally obtain the parameters required for such an analysis, by using performance monitoring counters. We compare our work against an existing approach and show that our approach outperforms it by providing tighter upper bounds on the number of bus requests generated by the tasks.
8th IEEE International Conference on Embedded Software and Systems (IEEE ICESS-11), IEEE, pp 1068-1075.