Towards the Certification of Multicore Platforms in the Avionics Domain
Ref: CISTER-TR-150716 Publication Date: 24 to 27, Mar, 2015
Towards the Certification of Multicore Platforms in the Avionics DomainRef: CISTER-TR-150716 Publication Date: 24 to 27, Mar, 2015
In the last decade, the semiconductor industry has experienced a paradigm shift from single core design to a multicore architecture era. This trend is driven by the fact that the increase in clock speed to enhance the performance of a core has hit a limit as the performance per watt became costly at high frequencies. A multicore processor (MCP) combines two or more cores into a single package (single or multiple dies) such that they can execute programs simultaneously. Although this feature is very appealing, it comes with new challenges, unfortunately. Most MCP platforms present many sources of unpredictability as the large majority of hardware vendors are mainly interested by improving the average performance of the system. This work discusses some sources of non-determinism and highlights the envisioned methodology to mitigate or eliminate their effect in the context of safety critical systems.
The 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015), WiP.