Trading Between Intra- and Inter-Task Cache Interference to Improve Schedulability
Ref: CISTER-TR-180803 Publication Date: 10 to 12, Oct, 2018
Trading Between Intra- and Inter-Task Cache Interference to Improve SchedulabilityRef: CISTER-TR-180803 Publication Date: 10 to 12, Oct, 2018
Caches help reduce the average execution time of tasks due to their fast operational speeds. However, caches may also severely degrade the timing predictability of the system due to intra- and inter-task cache interference. Intra-task cache interference occurs if the memory footprint of a task is larger than the allocated cache space or when two memory entries of that task are mapped to same space in cache. Inter-task cache interference occurs when memory entries of two or more distinct tasks use the same cache space. State-of-theart analysis focusing on bounding cache interference or reducing it by means of partitioning and by optimizing task layout in memory either focus on intra- or inter-task cache interference and do not exploit the fact that both intra- and inter-task cache interference can be interrelated. In this work, we show how one can model intra- and inter-task cache interference in a way that allows balancing their respective contribution to tasks worst-case response times. Since the placement of tasks in memory and their respective cache footprint determine the intra- and inter-task interference tasks may suﬀer, we propose a technique based on cache coloring to improve taskset schedulability. Experimental evaluation performed using a set of benchmarks show that our approach result in up to 14% higher taskset schedulability than state-of-the-art approaches.
26th International Conference on Real-Time Networks and Systems (RTNS 2018), pp 125-136.