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Geoffrey Nelissen (Publications)

Geoffrey Nelissen (Publications)

Geoffrey Nelissen (Publications)

PhD Université Libre de Bruxelles
Integrated PhD Researcher
May 2013-February 2020

Geoffrey Nelissen was born in Brussels, Belgium in 1985. He earned his MSc degree in Electrical Engineering at Université Libre de Bruxelles (ULB), Belgium in 2008. Then, he worked during four years as a PhD student in the PARTS research unit of ULB. In 2012, he received his PhD degree under the supervision of Professors Joël Goossens and Dragomir Milojevic, on the topic "Efficient Optimal Multiprocessor Scheduling Algorithms for Real-Time Systems". He is currently working at CISTER as a researcher scientist in the area of multiprocessor real-time scheduling theory. His research interests include real-time scheduling theory, real-time operating systems and multi-processors/multi-cores architectures.

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Conference or Workshop Papers
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling CISTER-TR-200801 
Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, Giorgio Buttazzo26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020). 21 to 24, Apr, 2020, pp 239-252. Online.
Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems CISTER-TR-191102 
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarDesign, Automation and Test in Europe Conference (DATE 2020). 9 to 13, Mar, 2020, pp 442-447. Online.
From Code to Weakly Hard Constraints: A Pragmatic End-to-End Toolchain for Timed C CISTER-TR-190905 
Saranya Natarajan, Mitra Nasri, David Broman, Björn B. Brandenburg, Geoffrey Nelissen40th IEEE Real-Time Systems Symposium (RTSS 2019). 18 to 21, Feb, 2020, pp 167-180. York, United Kingdom.RTSS 2019 originally postponed from December 2019 (Hong-Kong) to February 2020 (York, UK) was cancelled.
Technical Reports
Hoplitert*: Real-Time NoC for FPGA CISTER-TR-200702 
Yilian Ribot, Geoffrey NelissenAccepted in 2020.