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José Fonseca (Publications)

José Fonseca (Publications)

José Fonseca (Publications)

PhD University of Porto, Portugal
Collaborator PhD Researcher
February 2012 - February 2019

José Fonseca is a researcher at CISTER Research Unit. José earned his PhD in Electrical and Computer Engineering in January 2019 at the Faculty of Engineering of the University of Porto, Portugal. He also holds a degree (2010) and a Master's degree (2012) in Computer Engineering from the School of Engineering of the Polytechnic Institute of Porto, Portugal.

Since he joined CISTER in February 2012, his research activities are mostly related to the specification and analysis of real-time embedded systems, with particular emphasis on parallel applications. His main research interests include real-time operating systems, parallel programming models, real-time scheduling theory and multi-/many-core platforms.

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Thesis
Multiprocessor Scheduling and Mapping Techniques for Real-Time Parallel Applications CISTER-TR-190105 
José FonsecaPhD Thesis. 24, Jan, 2019. Porto.Presidente do Juri Doutor José Alfredo Ribeiro da Silva Matos, Professor Catedrático da FEUP
Vogais Doutor Robert Davis, Senior Research Fellow on the Department of Computer Science, on the University of York, United Kingdom; Doutor Eduardo Quinones Moreno, Senior Research on the Department of Computer Science, on the BSC - Barcelona Supercomputing Center, Spain; Doutor Vincent Nélis, Integrated Researcher, no CISTER – Instituto Superior de Engenharia do Porto /IPP (Orientador); Doutor Luis Miguel Pinho de Almeida, Professor Associado do Departamento de Engenharia Eletrotécnica e de Computadores da Faculdade de Engenharia da Universidade do Porto; Doutor Pedro Alexandre Guimarães Lobo Ferreira Souto, Professor Auxiliar do Departamento de Engenharia Informática da Faculdade de Engenharia da Universidade do Porto.

Supporting Intra-Task Parallelism in Real-Time Multiprocessor Systems CISTER-TR-121007 
José FonsecaMaster Thesis. Oct 2012. Porto.
Journal Papers
Schedulability Analysis of DAG Tasks with Arbitrary Deadlines under Global Fixed-Priority Scheduling CISTER-TR-190107 
José Fonseca, Geoffrey Nelissen, Vincent NélisReal-Time Systems, Springer. 2019, Volume 55, Issue 2, pp 387-432.
Conference or Workshop Papers
Improved Response Time Analysis of Sporadic DAG Tasks for Global FP Scheduling CISTER-TR-170901 
José Fonseca, Geoffrey Nelissen, Vincent NélisInternational Conference on Real-Time Networks and Systems 2017 (RTNS 2017). 4 to 6, Oct, 2017, pp 28-37. Grenoble, France.Outstanding Paper and Best Paper Awards
Response Time Analysis of Sporadic DAG Tasks under Partitioned Scheduling CISTER-TR-160502 
José Fonseca, Geoffrey Nelissen, Vincent Nélis, Luis Miguel Pinho11th IEEE International Symposium on Industrial Embedded Systems (SIES 2016). 23 to 25, May, 2016. Krakow, Poland.
Timing Analysis of Fixed Priority Self-Suspending Sporadic Tasks CISTER-TR-150506 
Geoffrey Nelissen, José Fonseca, Gurulingesh Raravi, Vincent Nélis27th Euromicro Conference on Real-Time Systems (ECRTS 2015). 7 to 10, Jul, 2015. Lund, Sweden.
Analysis of self-interference within DAG tasks CISTER-TR-150604 
José Fonseca, Vincent Nélis, Geoffrey Nelissen, Luis Miguel Pinho6th Real-Time Scheduling Open Problems Seminar (RTSOPS 2015). 7, Jul, 2015. Lund, Sweden.
A Multi-DAG Model for Real-Time Parallel Applications with Conditional Execution CISTER-TR-141207 
José Fonseca, Vincent Nélis, Gurulingesh Raravi, Luis Miguel PinhoThe 30th ACM/SIGAPP Symposium On Applied Computing (SAC 2015). 13 to 17, Apr, 2015, Embedded Systems. Salamanca, Spain.
How to deal with control-flow information in parallel real-time applications? CISTER-TR-141201 
José Fonseca, Vincent Nélis, Gurulingesh Raravi, Luis Miguel Pinho5th Real-Time Scheduling Open Problems Seminar (RTSOPS 2014). 8, Jul, 2014. Madrid, Spain.
The challenge of time-predictability in modern many-core architectures CISTER-TR-140624 
Vincent Nélis, Patrick Meumeu Yomsi, Luis Miguel Pinho, José Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, Andrea Marongiu14th International Workshop on Worst-Case Execution Time Analysis (WCET 2014). 8, Jul, 2014. Madrid, Spain.
On the use of Work-Stealing Strategies in Real-Time Systems CISTER-TR-130110 
Luis Miguel Nogueira, Luis Miguel Pinho, José Fonseca, Cláudio MaiaHigh-performance and Real-time Embedded Systems (HiRES 2013). 23, Jan, 2013. Berlin, Germany.In conjunction with the 8th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2013)
Dynamic Global Scheduling of Parallel Real-Time Tasks HURRAY-TR-121005 
Luis Miguel Nogueira, José Fonseca, Cláudio Maia, Luis Miguel Pinho10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2012). 5 to 7, Dec, 2012, pp 500-507. Paphos, Cyprus.
Real-Time Scheduling of Parallel Tasks in the Linux Kernel HURRAY-TR-120714 
José Fonseca, Luis Miguel Nogueira, Cláudio Maia, Luis Miguel PinhoSimpósio de Informática (INForum 2012). 6 to 7, Sep, 2012. Lisboa, Portugal.Best paper of the Real-time and Embedded Systems track.
Conference or Workshop Posters/Demos
Parallelising Real-Time Software CISTER-TR-140606 
Cláudio Maia, Luis Miguel Nogueira, José Fonseca, Luis Miguel Pinho, António BarrosPoster presented in CISTER 1st Industrial Workshop on Real-Time and Embedded Systems (CiWork 2013). 18, Jun, 2013. Porto, Portugal.
Technical Reports
Errata: Timing Analysis of Fixed Priority Self-Suspending Sporadic Tasks CISTER-TR-170205 
Geoffrey Nelissen, José Fonseca, Gurulingesh Raravi, Vincent Nélis2017.