Memory-Aware Scheduling of Mixed-Criticality Systems on Multicore Platforms
Ref: CISTER-TR-191201 Publication Date: 13, Dec, 2019
Memory-Aware Scheduling of Mixed-Criticality Systems on Multicore Platforms
Ref: CISTER-TR-191201 Publication Date: 13, Dec, 2019Abstract:
The role of mixed-criticality systems is increasing in the design of safety critical systems, especially
in avionics and automotive domains. Conventionally, these systems are designed as combination
of subsystems with different degree of importance and criticality. Modern common-of-theshelf
multicore platforms (COTS) offer significant advantages in terms of raw computing, energy
consumption and size (SWaP) allowing the integration these subsystems on a same platform. The
benefits of developing mixed-criticality systems on multicore processors are accompanied with
multitude of new issues. Most noticeably, the interference caused by the shared resources may
lead to unpredictable temporal behavior, jeopardizing the timing guarantees provided in isolation.
To address these challenges, new mixed-criticality models, memory interference protocols
and corresponding scheduling analysis techniques are needed to not only ensure the safety of the
system, but also to efficiently utilize the available resources of the modern COTS platforms.
This thesis research plan will explore a set of new solutions including: novel system models to
efficiently utilize the processing capacity of the platform, interference mitigation on shared channels,
exploration of news features of multicore platforms, such as multiple memory controllers,
isolation concerns usually imposed by the certification authorities and deep learning mechanisms
to address allocation problems.
Ishfaq HussainNotes: Comissão de acompanhamento: Comissão Científica PDEEC: José Silva Matos Orientador: Muhammad Ali Awan Coorientador: Konstantinos Bletsas Elemento da FEUP: Pedro Ferreira Souto Elemento externo: Dr. Rodolfo Pellizzoni (University of Waterloo, Canada)
Record Date: 12, Dec, 2019