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Mixed-criticality Scheduling with Memory Bandwidth Regulation
Ref: CISTER-TR-171201       Publication Date: 19 to 23, Mar, 2018

Mixed-criticality Scheduling with Memory Bandwidth Regulation

Ref: CISTER-TR-171201       Publication Date: 19 to 23, Mar, 2018

Abstract:
Mixed-criticality (MC) multicore system design must reconcile safety guarantees and high performance. The interference among cores on shared resources in such systems leads to unpredictable temporal behaviour. Memory bandwidth regulation among different cores can be a useful tool to mitigate the interference when accessing main memory. However, for mixed-criticality systems conforming to the (well-established) Vestal model, the existing schedulability analyses are oblivious to memory stalling effects, including stalls from memory bandwidth regulation. This makes it unsafe. In this paper, we address this issue by formulating a schedulability analysis for mixed-criticality fixed-priority-scheduled multicore systems using per-core memory access regulation. We also propose multiple heuristics for memory bandwidth allocation and task-to-core assignment. We implement our analysis and heuristics in a tool and evaluate them, performance-wise, through extensive experiments. Our experiments show that stall-oblivious schedulability analysis may be optimistic due to contention on shared memory resources.

Authors:
Muhammad Ali Awan
,
Pedro Souto
,
Konstantinos Bletsas
,
Benny Ã…kesson
,
Eduardo Tovar


Events:

DATE 2018
19, Mar, 2018 >> 23, Mar, 2018
Design, Automation and Test in Europe
Dresden, Germany


Accepted in Design, Automation and Test in Europe 2018 (DATE 2018).
Dresden, Germany.



Record Date: 5, Dec, 2017