Mixed-criticality scheduling with memory regulation

Muhammad Ali Awan; Konstantinos Bletsas; Pedro Souto; Benny Åkesson; Eduardo Tovar; Jibran Ali

Mixed-criticality scheduling with memory regulation
Ref: CISTER-TR-160604 Publication Date: 5 to 8, Jul, 2016

Mixed-criticality scheduling with memory regulation

Ref: CISTER-TR-160604 Publication Date: 5 to 8, Jul, 2016

Abstract:
The state-of-the-art models and schedulability analysis for mixed-criticality multicore systems overlook low-level aspects of the system. To improve their credibility, we therefore incorprate, in this work, the effects of delays from memory contention on a shared bus. Specifically, to that end, we adopt the predictable memory reservation mechanism proposed by the Single Core Equivalence framework. Additionally, we explore how the reclamation, for higher-criticality tasks, of cache resources allocated to lower-criticality tasks, whenever there is a criticality (mode) change in the system, can improve schedulability.

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