Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform
Ref: CISTER-TR-170302 Publication Date: 18 to 20, Apr, 2017
Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core PlatformRef: CISTER-TR-170302 Publication Date: 18 to 20, Apr, 2017
Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the offchip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms.
In this work, we target a state-of-the-art many-core processor, the Kalray MPPA. A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.
Accepted in 24th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2017).