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TACLe Summer School 2016

29, Jun, 2016

In late June, CISTER researcher Vincent Nelis gave a course on "WCET-aware parallel programming" at a summer school organized in Yspertal, Austria, by the ICT COST Action "TACLe". The objective of these lectures was to introduce young researchers to the types of timing requirements that are typically encountered in real-world applications, briefly survey the methodologies available for timing analysis, and weigh up their pros and cons under different contexts. The lectures were focused, in particular, on modern applications that are subject to strict timing constraints but are also extremely demanding in terms of computation-power and thus need to execute on powerful architectures in which workload can be parallelized. This combination of high-performance and real-time requirements comes as a new and exciting challenge for the research community. Practical examples were also shown with simple programs on the Kalray MPPA-256 development board, collecting runtime timed traces, and using analysis tools provided in the Kalray SDK to get WCET estimates.