Login

Vincent Nélis (Publications)

Vincent Nélis (Publications)

Vincent Nélis (Publications)

PhD Université Libre de Bruxelles, Belgium
Integrated PhD Researcher
November 2010 - January 2018

Vincent Nelis received his Ph.D. degree in 2010, at the age of 25, at the Computer Science Department of the Université Libre de Bruxelles, Belgium. Since then, he has graduated 2 Ph.D. students as main supervisor (both received the highest distinction for their thesis) and one Ph.D. student as co-supervisor. He is currently the main supervisor of a third Ph.D. student and co-supervises a second Ph.D. student.

Vincent Nelis has published more than 40 papers with about 50 different co-authors in international journals, conferences, and workshops. He received 7 awards, contributed to 9 R&D projects, led a Work Package in a European FP7 STREP project, chaired 3 international workshops, and he has been member of the program committee of more than 30 international journals, conferences and workshops. Throughout his short career he has given countless presentations and attended numerous meetings, from simple collaborations with academic peers to project meetings, technical and review meetings.

Currently, his main research interest is in developing methods and tools to derive all sorts of timing estimates for applications running on multicore platforms.

Journal Papers
P-SOCRATES: A parallel software framework for time-critical many-core systems CISTER-TR-151002 
Luis Miguel Pinho, Vincent Nélis, Patrick Meumeu Yomsi, Eduardo Quiñones, Marko Bertogna, Paolo Burgio, Andrea Marongiu, Claudio Scordino, Paolo Gai, Michele Ramponi, Michal Mardiak
ABSTRACT Additional Files: PDFPoster
Microprocessors and Microsystems (MICPRO), Elsevier. Nov 2015, Volume 39, Issue 8, pp 1190-1203.
Global and Partitioned Multiprocessor Fixed Priority Scheduling with Deferred Pre-emption CISTER-TR-150107 
Robert Davis, Alan Burns, José Marinho, Vincent Nélis, Stefan M. Petters, Marko BertognaTransactions on Embedded Computing Systems - Special Issue on Embedded Platforms for Crypto and Regular Papers (TECS), Article No 47, ACM. May 2015, Volume 14, Issue 3, pp 47:1-47:28. U.S.A..
Conference or Workshop Papers/Talks
A Generic and Compositional Framework for Multicore Response Time Analysis CISTER-TR-151003 
Sebastian Altmeyer, Robert Davis, Leandro Indrusiak, Claire Maiza, Vincent Nélis, Jan Reineke23rd International Conference on Real-Time Networks and Systems (RTNS 2015). 4 to 6, Nov, 2015, Main Track. Lille, France.Outstanding Paper Award
How realistic is the mixed-criticality real-time system model? CISTER-TR-151004 
Alexandre Esper, Geoffrey Nelissen, Vincent Nélis, Eduardo Tovar
ABSTRACTPDFPDF Additional Files: PDFPresentation
23rd International Conference on Real-Time Networks and Systems (RTNS 2015). 4 to 6, Nov, 2015, Main Track. Lille, France.Outstanding Paper Award
Real-time Parallel Applications on Many-core Architectures CISTER-TR-151206 
Luis Miguel Pinho, Vincent Nélis, Patrick Meumeu YomsiINForum - Simpósio de Informática (INFORUM 2015). 7 to 8, Sep, 2015. Portugal.
Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures CISTER-TR-150606 
Matthias Becker, Dakshina Dasari, Vincent Nélis, Moris Behnam, Luis Miguel Pinho, Thomas NolteThe Euromicro Conference on Digital System Design (DSD 2015). 26 to 28, Aug, 2015. Funchal, Portugal.
Methodologies for the WCET Analysis of Parallel Applications on Many-core Architectures CISTER-TR-150607 
Vincent Nélis, Patrick Meumeu Yomsi, Luis Miguel PinhoThe Euromicro Conference on Digital System Design (DSD 2015). 26 to 28, Aug, 2015. Funchal, Portugal.
Partitioning the Network-on-Chip to Enable Virtualization on Many-Core Processors CISTER-TR-150608 
Matthias Becker, Dakshina Dasari, Vincent Nélis, Moris Behnam, Thomas NolteThe 6th International Real-Time Scheduling Open Problems Seminar (RTSOPS 2015). 7, Jul, 2015. Lund, Sweden.
Timing Analysis of Fixed Priority Self-Suspending Sporadic Tasks CISTER-TR-150506 
Geoffrey Nelissen, José Fonseca, Gurulingesh Raravi, Vincent Nélis27th Euromicro Conference on Real-Time Systems (ECRTS 2015). 7 to 10, Jul, 2015. Lund, Sweden.
Analysis of self-interference within DAG tasks CISTER-TR-150604 
José Fonseca, Vincent Nélis, Geoffrey Nelissen, Luis Miguel Pinho6th Real-Time Scheduling Open Problems Seminar (RTSOPS 2015). 7, Jul, 2015. Lund, Sweden.
A Multi-DAG Model for Real-Time Parallel Applications with Conditional Execution CISTER-TR-141207 
José Fonseca, Vincent Nélis, Gurulingesh Raravi, Luis Miguel PinhoThe 30th ACM/SIGAPP Symposium On Applied Computing (SAC 2015). 13 to 17, Apr, 2015, Embedded Systems. Salamanca, Spain.
Towards Certifiable Multicore-based Platforms for Avionics CISTER-TR-150702 
Muhammad Ali Awan, Patrick Meumeu Yomsi, Konstantinos Bletsas, Vincent Nélis, Eduardo Tovar, Pedro SoutoWork in Progress Session, 21st IEEE Real-Time and Embedded Techonology and Applications Symposium (RTAS 2015). 13 to 16, Apr, 2015, pp 27-28. Seattle, U.S.A..
Towards the Certification of Multicore Platforms in the Avionics Domain CISTER-TR-150716 
Muhammad Ali Awan, Patrick Meumeu Yomsi, Konstantinos Bletsas, Vincent Nélis, Eduardo Tovar, Pedro Souto
ABSTRACTPDFPDF Additional Files: PDFPoster
Work in Progress Session, The 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 24 to 27, Mar, 2015. Porto, Portugal.
A system model and stack for the parallelization of time-critical applications on many-core architectures CISTER-TR-141206 
Vincent Nélis, Patrick Meumeu Yomsi, Luis Miguel Pinho, Eduardo Quiñones, Marko Bertogna, Andrea Marongiu, Paolo Gai, Claudio Scordino3rd Workshop on High-performance and Real-time Embedded Systems (HIRES 2015). 21, Jan, 2015. Amsterdam, Netherlands.
Conference or Workshop Posters/Demos
Using Quicktrace to collect runtime execution traces easily and automatically CISTER-TR-151208 
Vincent Nélis, Luis Miguel PinhoDemo in RTSS@Word Demo Session, IEEE Real-Time Systems Symposium (RTSS 2015). 1 to 4, Dec, 2015. U.S.A..