CISTER QuickNews - 17 Jun 2013

CISTER Quicknews

17, Jun, 2013


 CISTER QuickNews


Welcome to the June 17, 2013 edition of CISTER QuickNews.

CISTER QuickNews is a newsletter providing up-to-date information on the activities and results of the Research Centre in Real-Time and Embedded Computing Systems, being disseminated monthly to a selected audience.

For more information, contact us at cister-info@isep.ipp.pt, or visit www.cister.isep.ipp.pt. For the QuickNews archive, visit http://www.cister.isep.ipp.pt/quicknews/.

Quick look

1. TACLe Panel Of Experts Workshop On Programming Models For Parallel Architectures
2. CISTER Distinguished Seminar Series hosts Prof. Carlo Fischione
3. Training Workshop On The KALRAY's MPPA
4. PC Co-Chair Of The 26th Int.l Conf. Of Architecture Of Computing Systems (ARCS 2014)
5. ENCOURAGE Project Reaches An Important Milestone
6. ARTEMIS/FP7 CONCERTO Project Kick-Off Meeting

TACLe Panel Of Experts Workshop On Programming Models For Parallel Architectures

The EU COST Action on Timing Analysis on Code Level (TACLe) held its first Focussed Workshop at CISTER on the 21st of May. A COST Action is a funding mechanism which focuses on fostering exchange between researchers working on different research projects on national and international level on thematic commonalities. The TACLe COST Action involves researchers from 17 countries and such renown Universities as the University of York, UK, Mälardalen University, Sweden, or TU Vienna, Austria, to name but a few.

The focussed meeting organised by CISTER's Stefan M. Petters targeted parallel programming models in real-time systems and consequently their impact on code level timing analysis. It was structured around a set of talks by Ian Gray (University of York), Luís Miguel Pinho (CISTER), Raimund Kirner (University of Hertfordshire) Tullio Vardanega (University of Padua) interspersed with ample discussion time. Besides noteworthy speakers, the meeting was attended by PhD students from England, Sweden, Italy and a substantial number of CISTER researchers.

More info on TACLe: http://tacle.knossosnet.gr/


CISTER Distinguished Seminar Series hosts Prof. Carlo Fischione

Following o the tradition of previous Distinguished Seminar Series, Professor Carlo Fischione (KTH Royal Institute of Technology, Stockholm, Sweden) visited CISTER on May 9th to present a talk titled "Fast Distributed Non-convex and Convex Optimization over Wireless Sensor Networks".

Dr. Carlo Fischione is a tenured Associate Professor at KTH and ACCESS Linnaeus Center, Automatic Control Lab, Stockholm, Sweden. He held research positions at University of California at Berkeley, Berkeley, CA and Royal Institute of Technology, Stockholm, Sweden. He has co-authored over 80 publications, including book, book chapters, international journals and conferences, and an international patent. He received numerous awards, including the best paper award from the IEEE Transactions on Industrial Informatics, the Best Business Idea award from VentureCup East Sweden, 2010 and the Junior Research award from Swedish Research Council, 2007. He is co-founder and CTO of the sensor networks start-up company Aukoti.

More info at: http://www.cister.isep.ipp.pt/events/+distinguished+seminar+series/


Training Workshop On The KALRAY's MPPA

On May 6th-7th, took place in CISTER a training workshop on the KALRAY's MPPA (Multi-Purpose Processor Array) platform. This platform is a challenging many-core system, which provides a MPPA-256 processor (16 clusters of 16 work cores, together with a few more for platform management), and development environment both for posix and dataflow programming environments.

CISTER recently acquired some of these platforms, which will serve as advanced testbeds for the ongoing multi/many-core research activities, such as timing analysis, real-time scheduling of parallel tasks, operating systems and programming models.

This 2-day training in the platform was provided by 3 engineers from Kalray, covering the platforms architecture, and its development environments. CISTER is analyzing with Kalray the possibility to jointly tackle some of the identified challenges.

More information available at http://www.kalray.eu/products/mppa-developer/


PC Co-Chair Of The 26th Int.l Conf. Of Architecture Of Computing Systems (ARCS 2014)

CISTER Researcher Eduardo Tovar is to serve as Program Co-chair of the ARCS 2014 Architecture of Computing Systems conference to be held the University of Luebeck (Germany) on February 25-28, 2014 .

The ARCS series of conferences has over 30 years of tradition reporting top notch results in computer architecture and operating systems research. The focus of the 2014 conference will be on embedded computer systems connecting computing with the physical world. Like the previous conferences in this series, it continues to be an important forum for computer architecture research.

Further information at: http://www.arcs2014.iti.uni-luebeck.de/index.php


ENCOURAGE Project Reaches An Important Milestone

CISTER's researchers Luis Miguel Pinho and Michele Albano attended 28th/29th of May the ENCOURAGE general face-to-face assembly, which took place in the facilities of UPC, in Terrassa, Barcelona, Spain.

The ENCOURAGE project, of the FP7/ARTEMIS Embedded Computing Systems Initiative, aims to develop embedded intelligence and integration technologies that will directly optimize energy use in buildings with renewable energy and enable active participation in the future smart grid environment. Within the project, CISTER was responsible for the task specifying the overall architecture and it is one of the main drivers of the middleware messaging infrastructure.

Parallel to the general assembly, a technical meeting took place to finish the work on the initial release of the project middleware components, an important step to meet the project's 3rd Milestone (Integration Readiness). The ENCOURAGE GA also addressed the detailed planning of work for the implementation of the first demonstrator, which will take place in the 2nd year review, next October in Aalborg, Denmark.

More information at: http://www.encourage-project.eu/


ARTEMIS/FP7 CONCERTO Project Kick-Off Meeting

The Artemis CONCERTO project had its kickoff meeting on 13th and 14th of May, 2013 in Pisa, Italy, where CISTER's researchers Eduardo Tovar, Vincent Nelis, Geoffrey Nelissen and Gurulingesh Raravi participated.

CONCERTO will address emerging embedded systems platforms harnessing new heterogeneous, multicore architectures to enable the next generation of powerful mission-critical applications. The applicability of the CONCERTO solutions will be validated in the aerospace, telecoms, automotive, petroleum and medical industrial domains.

CISTER will have a bold participation in the CONCERTO project. CISTER will be central to the success of one of the main objectives of CONCERTO, which is extending the multicore domain the model driven engineering approach for critical software development that resulted from the recently finished CHESS FP7/Artemis project.

Besides ISEP (through CISTER/INESC-TEC), the CONCERTO project involves key industrial players such as Intecs (IT), Thales (FR), Atego (FR), EADS (FR), Aicas (DE), The Open Group (UK), Oilfield Technology Group (NO) and Critical Software (PT). From the EADS group both Airbus (aviation) and Astrium (satellites) are participating. CONCERTO is a 10 Million Euros cost project, out of which 4 Million Euros of funding (both EU and National funding). The total funding for ISEP will be 375 KEuros.

For more info on CONCERTO, please visit: http://www.cister.isep.ipp.pt/projects/concerto/

For more info on CHESS, please visit: http://www.chess-project.org/


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