CISTER QuickNews - 31 Mar 2014

CISTER Quicknews

31, Mar, 2014


 CISTER QuickNews

Welcome to the March 31, 2014 edition of CISTER QuickNews.

CISTER QuickNews is a newsletter providing up-to-date information on the activities and results of the Research Centre in Real-Time and Embedded Computing Systems, being disseminated monthly to a selected audience.

For more information, contact us at cister-info@isep.ipp.pt, or visit www.cister.isep.ipp.pt. For the QuickNews archive, visit http://www.cister.isep.ipp.pt/quicknews/.

Quick look

1. European Research Project DEWI Starts Off
2. CISTER Participates In A New Project On Validation Of Critical Systems
3. CISTER’s PhD Student Successfully Defends His Thesis
4. CISTER Distinguished Seminar Series Hosts Prof. Sanjoy Baruah

European Research Project DEWI Starts Off

The kickoff meeting of the Artemis project DEWI (Dependable Embedded Wireless Infrastructure) has taken place in Graz, on March 28-29.

DEWI (which has an overall budget of 18 million euro) will identify and implement an embedded wireless communication infrastructure that can replace traditional wired communication networks used in embedded systems in cars, airplanes, trains and buildings. DEWI is one of the biggest research efforts in Europe ever, gathering 58 European key players in the areas of embedded systems for transportation and building automation from 11 different countries. In terms of human resources, DEWI has the corresponding amount to 130 dedicated persons working fulltime for 3 years.

During the kickoff meeting, CISTER/INESC-TEC researcher Nuno Pereira lead the presentations of the Sub-Project dedicated to the Aeronautics domain (SP2), and was also deeply involved in the Interoperability domain (SP6), that is responsible for finding commonalities between the several application domains and for designing the high-level architecture of DEWI.

DEWI has special national relevance because it is the ARTEMIS project with the largest Portuguese consortium ever funded by the programme. Other than CISTER/INESC-TEC, Critical Software, Critical Materials and the GMV group (Skysoft) are part of the Portuguese Consortium in this project.

DEWI is a direct result of the effort developed by CISTER/INESC-TEC in the last open call for research projects in the strategic ARTEMIS initiative alongside with EMC2 (Embedded multi-core systems for mixed criticality applications in dynamic and changeable real-time environments) an Artemis Innovation Pilot Project (AIPP) which is deemed to start in April 2014. Both projects focus on applicability and industry and it is expected that it will encourage potential technology transfer activities in the future.

CISTER Participates In A New Project On Validation Of Critical Systems

CISTER/INESC-TEC is a partner of the V-SIS project which has been recently approved in the framework of the System of Incentives for Research and Technological Development (SI I&DT) of the National Strategic Reference Framework (QREN).

The V-SIS (Validation of Critical Systems) project proposes to address the challenge of critical systems validation through the creation of a validation competence centre, which will tackle the landscape of change and evolution in critical systems, triggered by normative evolutions like the recent ISO26262 (automotive) and the upgrade of DO-178C (avionics).

The V-SIS project proposes working two elemental vectors (1) functional safety and (2) critical systems validation. The work will be arranged in (i) processes innovation (RAMS techniques, model based V&V, multi-criticality systems, security fault injection) and (ii) validation laboratory development.

The project is led by Critical Software and includes CISTER/INESC-TEC and the CISUC research centre of the University of Coimbra. CISTER/INESC-TEC's role will be in the embedded real-time domain, in particular in what concerns the challenges introduced by the new multicore platforms.


CISTER’s PhD Student Successfully Defends His Thesis

CISTER/INESC-TEC PhD student Gurulingesh (Guru) Raravi has successfully defended his PhD thesis titled “Real-Time Scheduling on Heterogeneous Multicores”. Guru received his PhD with distinction from the University of Porto where he was enrolled in the PhD program jointly taught by CISTER/INESC-TEC and FEUP.

The main opponents where Prof. Sanjoy Baruah from the University of North Carolina, (USA) and Dr. Laurent George from the Laboratoire d'Informatique Gaspard-Monge at University of Paris-Est, France, both highly respected authorities in the field.

This work significantly enhanced the scheduling theory for heterogeneous multicores. Some of the specific problems addressed in this work, had no previous solutions and hence some of the proposed solutions in this work are first of their kind. Furthermore, for the problems where solutions existed before, the solutions proposed in this thesis are better than the existing solutions either in terms of the speedup factor or run-time complexity or average-case performance or a combination of these factors.

Throughout his work, Guru has managed to achieve recognition of his research as evidenced by the Outstanding paper award at 24th Euromicro Conference on Real-Time Systems (ECRTS 2012) and the Best paper award at 6th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2012). Besides these awards, results of his work were published in several reputed conferences such as RTSS 2010, RTSS 2012, ECRTS 2012, etc. and also in journals such as Real-Time Systems Journal 2013, 2014.

After this fruitful collaboration with CISTER/INESC-TEC for the last 4 years, Guru will now join the highly reputed Xerox Research Institute in Bangalore, India.



CISTER Distinguished Seminar Series Hosts Prof. Sanjoy Baruah

Professor Sanjoy K. Baruah from the University of North Carolina at Chapel Hill (U.S.A.) presented a talk titled “Scheduling Theory for Mixed-Criticality Systems” in the last CISTER/INESC-TEC Distinguished Seminar Series on March 11th.

In this presentation Prof. Sanjoy examined how scheduling theory is dealing with the recent trend in embedded systems towards implementing functionalities of different levels of importance (or criticalities) upon a shared platform. In the context of computer systems, scheduling theory seeks to ensure the efficient utilization of computing resources in order to optimize specified system-wide objectives. The talk also explored the factors that motivated this trend towards mixed-criticality systems, discussed how these systems pose new challenges to real-time scheduling theory, and described how real-time scheduling theory is responding to these challenges by devising new models and methods for the design and analysis of such systems.

Professor Sanjoy Baruah is a professor in the Department of Computer Science at the University of North Carolina at Chapel Hill. He received his PhD from the University of Texas at Austin in 1993. His research and teaching interests are in scheduling theory, real-time and safety-critical system design, and resource-allocation and sharing in distributed computing environments.

More information at: http://www.cister.isep.ipp.pt/events/sanjoy_k__baruah/




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